1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same, a bias is applied to a body in a silicon on insulator (SOI) MOSFET, effectively reducing or eliminating a floating body effect otherwise experienced by the semiconductor device.
2. Discussion of the Related Art
A conventional semiconductor device will be described hereinafter with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating a structure of a conventional SOI MOSFET.
As shown in FIG. 1, in an SOI MOSFET, an SOI substrate is formed by a SIMOX(Separation by IMplantation of OXygen) method, a BESOI(Bonded and Etchback SOI) method, or a smart-cut method.
The conventional MOSFET includes a buried oxide film 2 formed on a semiconductor substrate 1 at a thickness of 1000.about.4000 .ANG., an isolation layer 3 formed by LOCOS or STI process, surface silicon layers formed on the buried oxide film 2 at a thickness of 500.about.2000 .ANG.to form source/drain regions 4 and 6 and a channel region 5, a gate insulating film 7 formed on the channel region 5, a gate electrode 8 formed on the gate insulating film 7, an interleave insulating layer 9 formed on the gate electrode 8 and transistors of the source/drain regions 4 and 6 to selectively form a contact hole, and a metal electrode layer 10 connected to the source/drain regions 4 and 6 and the gate electrode 8 through the contact hole of the interleave insulating layer 9.
A thermal oxide film having a thickness of 50.about.100 .ANG., which is grown by thermal oxidation process, is mainly used as the gate insulating film 7.
An impurity ion is implanted into the channel region 5 to adjust a threshold voltage.
If the MOSFET is an NMOS transistor, B or BF.sub.2 is used as the impurity ion. Alternatively, if the MOSFET is a PMOS transistor, P or As is used as the impurity ion.
A doped polysilicon is mainly used as the gate electrode 8. If the MOSFET includes both NMOS and PMOS transistors, n.sup.+ type doped polysilicon may be used as the gate electrode 8. An n.sup.+ type doped polysilicon may also be used as the gate electrode 8 if the MOSFET is an NMOS transistor, but a p.sup.+ type doped polysilicon may be used as the gate electrode 8 if the MOSFET is a PMOS transistor.
After the gate electrode 8 is formed, the impurity ion is implanted to form the source/drain regions 4 and 6. For NMOS transistors, As is implanted at a dose of 2.about.5 E15 cm.sup.-2. For PMOS transistors, B or BF.sub.2 is implanted at a dose of 1.about.3 E15 cm.sup.-2.
At this time, a lightly doped drain (LDD) region may be formed to prevent the deterioration of device characteristic due to hot carriers.
The SOI device serves as a conventional bulk device. The channel region of the NMOS and PMOS transistors in these conventional MOSFET devices remains floating. Therefore, in the NMOS transistor, a floating body effect may be experienced since holes may accumulate in a body based on alpha particles or in the course of operating the device.
Due to this floating body effect, the conventional semiconductor device is susceptible to several problems. For instance, the breakdown voltage may be reduced by the floating body effect, and distortion may occur in Id-Vd curve, thereby deteriorating characteristic of the device. Further, an abnormal slope of subthreshold may occur and the operation of the device may become unstable due to transient effect in the course of AC operation.